/*************************************************************************/
/** This file and the information contain herein is provided "AS IS"    **/
/** without warranty of any kind, either expressed or implied,          **/
/** including but not limited to the implied warranties of              **/
/** merchantability and/or fitness for a particular purpose.            **/
/**                                                                     **/
/** This code cannot be redistributed or reused in any form whatsoever  **/
/** without the explicit approval of QPixel Technology Inc.             **/
/**                                                                     **/
/** Copyright (C) 2004 QPixel Technology Inc                            **/
/** All rights reserved.                                                **/
/*************************************************************************/
//----------------------------------------------------------------------------
// Hci.h
//
// Description: 
//
// Author: 
//	David Tao
//
//----------------------------------------------------------------------------

#define DMA_MAX_SIZE				0x03FFFF
#define QL201_VID_FW_START_ADDR		0x0
#define QL201_AUD_FW_START_ADDR		0x100000


// Host control interface registers
//
#define REG_HCI_INTERRUPT_ENABLE			0x00
#define REG_HCI_INTERRUPT_STATUS			0x01
#define REG_HCI_SETUP_MODE					0x02
#define REG_HCI_CONTROL						0x03
#define REG_HCI_REGISTER_ADDR_0				0x08
#define REG_HCI_REGISTER_ADDR_1				0x09
#define REG_HCI_REGISTER_DATA_0				0x0A
#define REG_HCI_REGISTER_DATA_1				0x0B
#define REG_HCI_REGISTER_DATA_2				0x0C
#define REG_HCI_REGISTER_DATA_3				0x0D
#define REG_HCI_MEMORY_ADDR_0				0x0E
#define REG_HCI_MEMORY_ADDR_1				0x0F
#define REG_HCI_MEMORY_ADDR_2				0x10
#define REG_HCI_MEMORY_ADDR_3				0x11
#define REG_HCI_MEMORY_DATA_0				0x12
#define REG_HCI_MEMORY_DATA_1				0x13
#define REG_HCI_MEMORY_DATA_2				0x14
#define REG_HCI_MEMORY_DATA_3				0x15
#define REG_HCI_SLAVE_MODE_WR_CYCLE_CNT		0x16


#define INT_ENABLE_ARM_MASK         0x01
#define INT_ENABLE_P2M_MASK         0x02
#define INT_ENABLE_M2P_MASK         0x04


#define INT_STATUS_ARM_MASK         0x01
#define INT_STATUS_P2M_MASK         0x02
#define INT_STATUS_M2P_MASK         0x04


#define SETUP_MODE_WIDTH_MASK       0x01
#define SETUP_MODE_INTERL_MASK      0x02
#define SETUP_MODE_SLAVE_MASK       0x04
#define SETUP_MODE_ENDIAN_MASK      0x08


#define QL_CTRL_ARM_MASK            0x01


#define SLAVE_MODE_WR_CNT_MASK      0xFF


#define REG_P2M_DMA_ADDR					0x0640
#define REG_P2M_DMA_LENGTH					0x0644
#define REG_M2P_DMA_ADDR					0x0648
#define REG_M2P_DMA_LENGTH					0x064C

/*  EOF : hci.h  */
