#include "PalmType.h"
#include "PalmChip.h"
#include "Ac97.h"
#include "Palm1lib.h"

#include <reg52.h>

void Ac97WriteReg(UCHAR iAddr, UCHAR iDataHi, UCHAR iDataLo)
{
	DCHAR i, iCount;

	EA = 0;		// disable all interrupts

	Ac97StopCodec();
//	XBYTE[AC97_DASLOT] = 0;
	XBYTE[AC97_CMDADDRL] = 0;
	XBYTE[AC97_CMDADDRH] = iAddr;
	XBYTE[AC97_CMDDATAL] = iDataLo;
	XBYTE[AC97_CMDDATAH] = iDataHi;
	for (i = 0; i < 2; i ++)
	{
		XBYTE[AC97_DASLOT] = 0xe0;
		XBYTE[AC97_DASLOT] = 0xe0;
		XBYTE[AC97_DASLOT] = 0xe0;
		iCount = 0;
		do
		{
			iCount ++;
			if (!iCount)	break;
		} while(XBYTE[AC97_DASLOT] & 0xc0);
	}

	XBYTE[AC97_CMDADDRH] = 0;
	XBYTE[AC97_CMDDATAL] = 0;
	XBYTE[AC97_CMDDATAH] = 0;
	Ac97StartCodec();

//	for (i = 0; i < 8; i ++)
//	{
//		XBYTE[AC97_DASLOT] = 0x88;	// Set right channel slots valid 
//	}

	EA = 1;
}

/*
void Ac97WriteReg(UCHAR iAddr, UCHAR iDataHi, UCHAR iDataLo)
{
	DCHAR i, iCount;

	i = 0;
	do
	{
		i ++;
		if (!i)	break;

		XBYTE[AC97_CMDADDRL] = 0;
		XBYTE[AC97_CMDADDRH] = iAddr;
		XBYTE[AC97_CMDDATAL] = iDataLo;
		XBYTE[AC97_CMDDATAH] = iDataHi;
		XBYTE[AC97_DASLOT] = 0xe0;
		iCount = 0;
		do
		{
			iCount ++;
			if (!iCount)	break;
		} while(XBYTE[AC97_DASLOT] & 0x40);
	} while (!iCount);

	XBYTE[AC97_DASLOT] = 0x88;	// Set right channel slots valid 
}


UCHAR Ac97ReadReg(UCHAR iAddr, BOOLEAN bHiByte)
{
	DSHORT iCount;

	XBYTE[AC97_CMDADDRL] = 0;
	XBYTE[AC97_CMDADDRH] = iAddr;
	XBYTE[AC97_DASLOT] = 0xc0;
	iCount = 0;
	do
	{
		iCount ++;
		if (!iCount)	break;
	} while ((XBYTE[AC97_ADSLOT] & 0x60) != 0x60);
	if (bHiByte)
	{
		return XBYTE[AC97_STATDATAH];
	}
	return XBYTE[AC97_STATDATAL];
}
*/

/*
;----------------------------------------------------------------------------------
;	void Ac97WriteReg(UCHAR iAddr, UCHAR iDataHi, UCHAR iDataLo)
;----------------------------------------------------------------------------------
_Ac97WriteReg:		
              ; Register R7 is assigned to parameter iAddr
              ; Register R5 is assigned to parameter iDataHi
              ; Register R3 is assigned to parameter iDataLo
                                           ; SOURCE LINE # 10 
	MOV    DPTR,#0B104H
	CLR    A
	MOVX   @DPTR,A
                                           ; SOURCE LINE # 11 
;	MOV    DPTR,#0B105H
	INC    DPL
	MOV    A,R7
	MOVX   @DPTR,A
                                           ; SOURCE LINE # 12 
;	MOV    DPTR,#0B106H
	INC    DPL
	MOV    A,R3
	MOVX   @DPTR,A
                                           ; SOURCE LINE # 13 
;	MOV    DPTR,#0B107H
	INC    DPL
	MOV    A,R5
	MOVX   @DPTR,A
                                           ; SOURCE LINE # 14 
	MOV    DPTR,#0B100H
	MOV    A,#0E0H
	MOVX   @DPTR,A
WHILE1:
                                           ; SOURCE LINE # 15 
;	MOV    DPTR,#0B100H
	MOVX   A,@DPTR
	JB     ACC.6,WHILE1
NXT1:
	RET    
*/

/*

void Ac97WriteReg(UCHAR iAddr, UCHAR iDataHi, UCHAR iDataLo)
{
	XBYTE[AC97_CMDADDRL] = 0;
	XBYTE[AC97_CMDADDRH] = iAddr;
	XBYTE[AC97_CMDDATAL] = iDataLo;
	XBYTE[AC97_CMDDATAH] = iDataHi;
	XBYTE[AC97_DASLOT] = 0xe0;
	while(XBYTE[AC97_DASLOT] & 0x40);
}

UCHAR Ac97ReadReg(UCHAR iAddr, BOOLEAN bHiByte)
{
	XBYTE[AC97_CMDADDRL] = 0;
	XBYTE[AC97_CMDADDRH] = iAddr;
	XBYTE[AC97_DASLOT] = 0xc0;
	while ((XBYTE[AC97_ADSLOT] & 0x60) != 0x60);
	if (bHiByte)
	{
		return XBYTE[AC97_STATDATAH];
	}
	return XBYTE[AC97_STATDATAL];
}

// Input codec data, begin DMA to codec
void Ac97Input(UCHAR iDmaHi, UCHAR iDmaLo, UCHAR iSdramIndex)
{
	XBYTE[DMA7_START_ADDR2] = iSdramIndex;
	XBYTE[DMA7_START_ADDR3] = AC97_IN_SDRAM_HI;
	XBYTE[DMA7_HIGH] = iDmaHi;
	XBYTE[DMA7_X1] = iDmaLo;		
//	XBYTE[DMA7_Y1] = 0;					// can be omitted
	XBYTE[DMA7_START_ADDR1] = 0;		// startup DMA
}

// Output codec data, begin DMA to codec
void Ac97Output(UCHAR iDmaHi, UCHAR iDmaLo, UCHAR iSdramIndex)
{
	if (XBYTE[SDRAM_STATUS1] & 0x20)
	{
		XBYTE[SDRAM_STATUS1] = 0x20;	// Stop previous SDRAM transfer first
	}

	XBYTE[DMA6_START_ADDR2] = iSdramIndex;
	XBYTE[DMA6_START_ADDR3] = AC97_OUT_SDRAM_HI;
	XBYTE[DMA6_HIGH] = iDmaHi;
	XBYTE[DMA6_X1] = iDmaLo;	
//	XBYTE[DMA6_Y1] = 0;				// can be omitted
	XBYTE[DMA6_START_ADDR1] = 0;		// startup DMA
}

void Ac97StartCodec()
{
	// start codec transfer 
	XBYTE[AC97_DASLOT] = 0x88;	// Set right channel slots valid 
	XBYTE[AC97_ADVAL] = 0x1;	// right channels valid 	
//	XBYTE[AC97_DASLOT] = 0x98;	// Set both channel slots valid 
//	XBYTE[AC97_ADVAL] = 0x3;	// both channels valid 	

}

void Ac97StopCodec()
{
//	XBYTE[SDRAM_STATUS1] = 0x60;	// Stop previous SDRAM transfer, if any
	XBYTE[AC97_DASLOT] = 0;
	XBYTE[AC97_ADVAL] = 0;
}

BOOLEAN Ac97CheckIrq()
{
	if (XBYTE[SDRAM_DMA_INT1] & DMA_MASK_AC97_IN) // DMA 7, ac97 input
	{
		XBYTE[SDRAM_DMA_INT1] = DMA_MASK_AC97_IN;
		return TRUE;
	}
	return FALSE;
}
*/

