#include "PalmType.h"
#include "PalmChip.h"
#include "p_util.h"

volatile BOOLEAN Dsp_bFinished;

void DspExecuteAndWait(USHORT iAddr)
{
	Dsp_bFinished = FALSE;

//	XBYTE[CMDQ_DL] = (UCHAR)iAddr; 
//	XBYTE[CMDQ_DH] = P_HIBYTE(iAddr)|0x80;
	DspExecute(iAddr);
	while (!Dsp_bFinished);
}

void DspDownloadCode(UCHAR iIndexHigh, UCHAR iIndexLow, USHORT iSize)
{
	DSHORT iPos;
	DCHAR i;
	PXSHORT pDataCacheS;

	XBYTE[CMDQ_PCH] &= 0xbf;			// 8032 control command queue
	XBYTE[CMDQ_DL] = 0x00;				// reset DSP
	XBYTE[CMDQ_DH] = 0x20;				// reset DSP 

	iPos = 0;
	iSize += SRAM_DMA_HALF_DWORD - 1;
	while (iSize > SRAM_DMA_HALF_DWORD)
	{
		SdramRead(iIndexHigh, iIndexLow, SRAM_DMA_HALF_DWORD);
		pDataCacheS = (PXSHORT)SRAM_DMA_START;
		for (i = 0; i < SRAM_DMA_HALF_DWORD; i ++)
		{
			if (iPos)
			{
				DspWritePMIn(iPos, pDataCacheS[1], pDataCacheS[0]);
			}
			pDataCacheS += 2;
			iPos ++;
		}
		iSize -= SRAM_DMA_HALF_DWORD;
		iIndexLow ++;
	}
/*	SdramRead(iIndexHigh, iIndexLow, (UCHAR)iSize);
	pDataCacheS = (PXSHORT)SRAM_DMA_START;
	for (i = 0; i < (UCHAR)iSize; i ++)
	{
		if (iPos)
		{
			DspWritePMIn(iPos, pDataCacheS[1], pDataCacheS[0]);
		}
		pDataCacheS += 2;
		iPos ++;
	}
*/
	DspWritePMIn(0, 0, 0);				// Start DSP by loading into IDMA 0

	XBYTE[CMDQ_CS] = 1;					// clear command queue
	XBYTE[CMDQ_PCL] = 0x18;				// Set DSP PC to 0x18
	XBYTE[CMDQ_PCH] = 0;				// Set DSP PC to 0x18
	XBYTE[CMDQ_PCH] |= 0x40;			// DSP control command queue
}



