// The header for modem uart registers

#ifndef __AT_MODEM_H
#define __AT_MODEM_H

#define MODEM_BASE  0x5400
#define MODEM_THR	0
#define MODEM_RBR   0
#define MODEM_DLL   0
#define MODEM_DLM   1
#define MODEM_IER   1
#define MODEM_FCR   2
#define MODEM_IIR   2
#define MODEM_LCR   3
#define MODEM_MCR   4
#define MODEM_LSR   5
#define MODEM_MSR   6
#define MODEM_SCR   7

#define MCR_VALUE     0x0b              // Modem control register
                                        //  0(DTR) : Data terminal ready
                                        //  1(RTS) : Request to send
                                        //  2() : Output 1
                                        //  3() : Output 2
                                        //  4() : Local loopback
                                        //  5() : -
                                        //  6() : -
                                        //  7() : -

#define LCR_VALUE     0x03              // Line control register
                                        //  0(WLS0) : Word length select 0
                                        //  1(WLS1) : Word length select 1
                                        //  2(STB) : Number of stop bits
                                        //  3(PEN) : Enable parity
                                        //  4(EPS) : Even parity select
                                        //  5() : Stick parity
                                        //  6() : Set break
                                        //  7(DLAB) : Divisor latch access bit

#define FCR_VALUE     0xc1              // FIFO control register
                                        //  0() : FIFO enable
                                        //  1() : RX FIFO reset
                                        //  2() : TX FIFO reset
                                        //  3() : DMA mode select
                                        //  4() : -
                                        //  5() : -
                                        //  6() : RX FIFO trigger level
                                        //  7() : RX FIFO trigger level
                                        // Enable FIFO, RX Trigger at 14 chars


#define IER_VALUE     0x05              // Interrupt enable register
                                        //  0(ERBFI) : Enable receiver data
                                        //              available interrupt and
                                        //              character timeout in
                                        //              FIFO mode
                                        //  1(ETBEI) : Enable transmitter
                                        //              holding register empty
                                        //              interrupt
                                        //  2(ELSI)  : Enable receiver line
                                        //              status interrupt
                                        //  3(EDSSI) : Enable modem status
                                        //              interrupt
                                        //  4() : -
                                        //  5() : -
                                        //  6() : -
                                        //  7() : -

#define DLM_VALUE     0x00              // Divisor latch MSB register
#define DLL_VALUE     0x01              // Divisor latch LSB register
                                        // Set 115200
#define MSR_DSR_OR_MASK		0x20	// 00100000, MSR's bit 5 
#define MCR_DTR_AND_MASK	0xfe	// 11111110, MCR's bit 0 
#define MCR_DTR_OR_MASK		0x01	


#define MODEM_RXD_FIFO_TRIGGER      14
#define MODEM_TXD_FIFO_SIZE         16

#define MODEM_BUF_SIZE		20
#define MODEM_BUF_LENGTH	16
#define MODEM_BUF_DWORD		5

#endif // __AT_MODEM_H
