// The header for Palm1 chip.

#ifndef _PALMCHIP_
#define _PALMCHIP_

// ALI 8051 Extensions
sfr DPL1   = 0x84;
sfr DPH1   = 0x85;
sfr DPS    = 0x86;
sfr CKCON  = 0x8E;

// Registers of Palm1

/*		PLL and CLOCK REGISTERS		*/ 
#define PLL_CTRL        0x8000 
#define PLL_BYPASS      0x8001 
#define PLL1_SUP        0x8002 
#define PLL1_SDN        0x8003 
#define PLL1_MODE       0x8004 
#define CLK_ENAB1       0x8005 
#define CLK_ENAB2       0x8006 
#define CLK_IDLE        0x8007 
#define CLK_TIMER1      0x8008 
#define CLK_TIMER2      0x8009 
#define PLL2_SUP        0x800A 
#define PLL2_SDN        0x800B 
#define PLL2_MODE       0x800C 
#define PLL_CONWS       0x800D 
#define CLK_SWITCH      0x800E 

/*		CmdQueue REGISTERS		*/ 
#define CMDQ_DL         0x8010
#define CMDQ_DH         0x8011 
#define CMDQ_CS         0x8012 
#define CMDQ_PCL        0x8014 
#define CMDQ_PCH        0x8015 

/* Systerm Reset REGISTERS */
#define SYS_RESET1      0x8020
#define SYS_RESET2      0x8021

/* Page REGISTERS */
#define PROG_PAGE       0x8100
#define CLR_PAGE_INT    0x8101 
#define PROG_DATA_MODE  0x8102 
#define DATA_PAGE       0x8103 

/* Interrupt, I/O registers */
#define INT_EDGE        0x8104 
#define INT_ENABLE      0x8105 
#define INT_CLR         0x8106 
#define INT_VALUE       0x8107 
#define KEY_DIN         0x8108 
#define KEY_DOUT        0x8109 
#define KEY_ENABLE      0x810A 
#define KEY_INTEN       0x810B 
#define KEY_INTCLR      0x810C 
#define KEY_EDGE        0x810D 
#define KEY_INVERT      0x810E 
#define IO_LO_DIN       0x8110 
#define IO_LO_DOUT      0x8111 
#define IO_LO_ENABLE    0x8112 
#define IO_LO_INTEN     0x8113 
#define IO_LO_INTCLR    0x8114 
#define IO_LO_EDGE      0x8115 
#define IO_LO_INVERT    0x8116 
#define IO_HI_DIN       0x8118 
#define IO_HI_DOUT      0x8119 
#define IO_HI_ENABLE    0x811A 
#define IO_HI_INTEN     0x811B 
#define IO_HI_INTCLR    0x811C 
#define IO_HI_EDGE      0x811D 
#define IO_HI_INVERT    0x811E 

#define IO_HHI_DIN      0x8120 
#define IO_HHI_DOUT     0x8121 
#define IO_HHI_ENABLE   0x8122 
#define IO_HHI_INTEN    0x8123 
#define IO_HHI_INTCLR   0x8124 
#define IO_HHI_EDGE     0x8125 
#define IO_HHI_INVERT   0x8126 

#define USB_SENSE       0x8138 
#define PFLASH_IDLE     0x813C 
#define DSP_INT_EN      0x813D 

/* Sharing blocks */
#define CODEC_SHARE     0x8040
#define STEREO_CLR      0x8042 
#define P128_SEL        0x8045 

/* RS232 pin mux */
#define RS232_MUX       0x8044
#define PFLASH_IO_IN    0x8130 
#define PFLASH_IO_OUT   0x8131 
#define PFLASH_IO_EN    0x8132 

/*		SDRAM interface REGISTERS		*/ 
#define SDRAM_INIT      0x9000

#define SDRAM_STATUS1   0x9001 
#define SDRAM_STATUS2   0x9002 

#define SDRAM_CON_REQ   0x9004 
#define SDRAM_DSP_REQ   0x9005 
#define SDRAM_DMA_MTL   0x9008 

#define SDRAM_BYTE_OP   0x9009 

#define SDRAM_REFL      0x9010 
#define SDRAM_REFH      0x9011 

#define SDRAM_DMA_INT1  0x9020 
#define SDRAM_DMA_INT2  0x9021 

#define SDRAM_DMA_EN1   0x9024 
#define SDRAM_DMA_EN2   0x9025 

#define SDRAM_WID0L     0x9030 
#define SDRAM_WID0H     0x9031 

#define SDRAM_WID1L     0x9032 
#define SDRAM_WID1H     0x9033 

#define SDRAM_WID2L     0x9034 
#define SDRAM_WID2H     0x9035 

#define SDRAM_WID3L     0x9036 
#define SDRAM_WID3H     0x9037 

/*		DMA REGISTERS		*/
/*DMA 1: Handsprint/DataFlash Output*/
#define DMA1_START_ADDR1    0x9100  // 0~7 bits
#define DMA1_START_ADDR2    0x9101  // 8~15 bits
#define DMA1_START_ADDR3    0x9102  // 16~21 bits
#define DMA1_HIGH           0x9103 
#define DMA1_X1             0x9104 
#define DMA1_Y1             0x9108 

/*DMA 2: Handsprint/DataFlash Inuput*/
#define DMA2_START_ADDR1    0x9110  // 0~7 bits
#define DMA2_START_ADDR2    0x9111 	// 8~15 bits
#define DMA2_START_ADDR3    0x9112 	// 16~21 bits
#define DMA2_HIGH           0x9113 
#define DMA2_X1             0x9114 
#define DMA2_Y1             0x9118 


/*DMA 3: Camera Input*/
#define DMA3_START_ADDR1    0x9120	// 0~7 bits
#define DMA3_START_ADDR2    0x9121 	// 8~15 bits
#define DMA3_START_ADDR3    0x9122 	// 16~21 bits
#define DMA3_HIGH           0x9123 
#define DMA3_X1             0x9124 
#define DMA3_Y1             0x9128 


/*DMA 4: Codec1 Output*/
#define DMA4_START_ADDR1    0x9130	// 0~7 bits
#define DMA4_START_ADDR2    0x9131 	// 8~15 bits
#define DMA4_START_ADDR3    0x9132 	// 16~21 bits
#define DMA4_HIGH           0x9133 
#define DMA4_X1             0x9134 
#define DMA4_Y1             0x9138 


/*DMA 5: Not used*/


/*DMA 6: Codec0/USB Output*/
#define DMA6_START_ADDR1    0x9150	// 0~7 bits
#define DMA6_START_ADDR2    0x9151 	// 8~15 bits
#define DMA6_START_ADDR3    0x9152 	// 16~21 bits
#define DMA6_HIGH           0x9153 
#define DMA6_X1             0x9154 
#define DMA6_Y1             0x9158 


/*DMA 7: Codec0/USB Input*/
#define DMA7_START_ADDR1    0x9160	// 0~7 bits
#define DMA7_START_ADDR2    0x9161 	// 8~15 bits
#define DMA7_START_ADDR3    0x9162 	// 16~21 bits
#define DMA7_HIGH           0x9163 
#define DMA7_X1             0x9164 
#define DMA7_Y1             0x9168 


/*DMA 9: Controller1*/
#define DMA9_START_ADDR1    0x9180	// 0~7 bits
#define DMA9_START_ADDR2    0x9181 	// 8~15 bits
#define DMA9_START_ADDR3    0x9182 	// 16~21 bits
#define DMA9_HIGH           0x9183 
#define DMA9_X1             0x9184 
#define DMA9_Y1             0x9188 


/*DMA 10: Controller2*/
#define DMA10_START_ADDR1   0x9190	// 0~7 bits
#define DMA10_START_ADDR2	0x9191 // 8~15 bits
#define DMA10_START_ADDR3	0x9192 // 16~21 bits
#define DMA10_HIGH          0x9193 
#define DMA10_X1            0x9194 
#define DMA10_Y1            0x9198 


/*DMA 11: PM1*/
#define DMA11_START_ADDR1   0x91a0	// 0~7 bits
#define DMA11_START_ADDR2   0x91a1 // 8~15 bits
#define DMA11_START_ADDR3   0x91a2 // 16~21 bits
#define DMA11_HIGH          0x91a3 
#define DMA11_X1            0x91a4 
#define DMA11_Y1            0x91a8 


/*DMA 12: PM2*/
#define DMA12_START_ADDR1   0x91b0	// 0~7 bits
#define DMA12_START_ADDR2   0x91b1 // 8~15 bits
#define DMA12_START_ADDR3   0x91b2 // 16~21 bits
#define DMA12_HIGH          0x91b3 
#define DMA12_X1            0x91b4 
#define DMA12_Y1            0x91b8 


/*DMA 13: DM1*/
#define DMA13_START_ADDR1   0x91c0	// 0~7 bits
#define DMA13_START_ADDR2   0x91c1	// 8~15 bits
#define DMA13_START_ADDR3   0x91c2	// 16~21 bits
#define DMA13_HIGH          0x91c3 
#define DMA13_X1            0x91c4 
#define DMA13_Y1            0x91c8 


/*DMA 14: DM2*/
#define DMA14_START_ADDR1   0x91d0  // 0~7 bits
#define DMA14_START_ADDR2   0x91d1  // 8~15 bits
#define DMA14_START_ADDR3   0x91d2  // 16~21 bits
#define DMA14_HIGH          0x91d3 
#define DMA14_X1            0x91d4 
#define DMA14_Y1            0x91d8 


/*		FIFO REGISTERS		*/
/*Channel 1*/
#define CHN1_START_ADDR     0x9300
#define CHN1_END_ADDR       0x9301 
#define CHN1_HIGH_CHECK     0x9302 
#define CHN1_LOW_CHECK      0x9303 
#define CHN1_STOP_CHECK     0x9304 
/*Channel 1*/
/*Channel 2*/
#define CHN2_START_ADDR     0x9308
#define CHN2_END_ADDR       0x9309 
#define CHN2_HIGH_CHECK     0x930a 
#define CHN2_LOW_CHECK      0x930b 
#define CHN2_STOP_CHECK     0x930c 
#define CHN2_FLUSH          0x930d 
/*Channel 2*/
/*Channel 3*/
#define CHN3_START_ADDR     0x9310
#define CHN3_END_ADDR       0x9311 
#define CHN3_HIGH_CHECK     0x9312 
#define CHN3_LOW_CHECK      0x9313 
#define CHN3_STOP_CHECK     0x9314 
#define CHN3_FLUSH          0x9315 
/*Channel 3*/
/*Channel 4*/
#define CHN4_START_ADDR     0x9318
#define CHN4_END_ADDR       0x9319 
#define CHN4_HIGH_CHECK     0x931a 
#define CHN4_LOW_CHECK      0x931b 
#define CHN4_STOP_CHECK     0x931c 
/*Channel 4*/
/*Channel 5*/
#define CHN5_START_ADDR     0x9320
#define CHN5_END_ADDR       0x9321 
#define CHN5_HIGH_CHECK     0x9322 
#define CHN5_LOW_CHECK      0x9323 
#define CHN5_STOP_CHECK     0x9324 
/*Channel 5*/
/*Channel 6*/
#define CHN6_START_ADDR     0x9328
#define CHN6_END_ADDR       0x9329 
#define CHN6_HIGH_CHECK     0x932a 
#define CHN6_LOW_CHECK      0x932b 
#define CHN6_STOP_CHECK     0x932c 
/*Channel 6*/
/*Channel 7*/
#define CHN7_START_ADDR     0x9330
#define CHN7_END_ADDR       0x9331 
#define CHN7_HIGH_CHECK     0x9332 
#define CHN7_LOW_CHECK      0x9333 
#define CHN7_STOP_CHECK     0x9334 
/*Channel 7*/

/*		SRAM buffer REGISTERS		*/
#define SRAM_CON_SWAP       0xa000
#define SRAM_CON_CH1ADDRL   0xa001 
#define SRAM_CON_CH1ADDRH   0xa002 
#define SRAM_CON_CH2ADDRL   0xa003 
#define SRAM_CON_CH2ADDRH   0xa004 

#define SRAM_BYTE_OP        0xa005 

#define SRAM_DM_PM_CTRL     0xa008 
#define SRAM_DM_CH1ADDRL    0xa009 
#define SRAM_DM_CH1ADDRH    0xa00a 
#define SRAM_DM_CH2ADDRL    0xa00b 
#define SRAM_DM_CH2ADDRH    0xa00c 

#define SRAM_DSP_RET        0xa010 
#define SRAM_DSP_RET_LO     0xa011 

/*0xa014 #define SRAM_PM_MODE;*/
#define SRAM_PM_CH1ADDRL    0xa015
#define SRAM_PM_CH1ADDRH    0xa016 
#define SRAM_PM_CH2ADDRL    0xa017 
#define SRAM_PM_CH2ADDRH    0xa018 

/*		SPORT1 interface REGISTERS		*/
#define UDA_MODE_SET        0xb000
#define UDA_CLOCK_SET       0xb001 

#define UDA_L3CLK           0xb008 
#define UDA_L3DATA          0xb009 

#define AC97_DASLOT         0xb100 
#define AC97_ADVAL          0xb102 
#define AC97_WARMWAKE       0xb103 
#define AC97_CMDADDRL       0xb104 
#define AC97_CMDADDRH       0xb105 
#define AC97_CMDDATAL       0xb106 
#define AC97_CMDDATAH       0xb107 
#define AC97_ADSLOT         0xb108 
#define AC97_STATADDRL      0xb10C 
#define AC97_STATADDRH      0xb10D 
#define AC97_STATDATAL      0xb10E 
#define AC97_STATDATAH      0xb10F 


/*		Camera interface REGISTERS		*/
#define CAM_XCOUNTL     0xb200
#define CAM_XCOUNTH     0xb201 

#define CAM_YCOUNTL     0xb202 
#define CAM_YCOUNTH     0xb203 

#define CAM_IO_EN       0xb204 
#define CAM_IO_DATA     0xb205 

#define CAM_YINTL       0xb206 
#define CAM_YINTH       0xb207 

#define CAM_XSTARTL     0xb208 
#define CAM_XSTARTH     0xb209 

#define CAM_YSTARTL     0xb20a 
#define CAM_YSTARTH     0xb20b 

#define CAM_XENDL       0xb20c 
#define CAM_XENDH       0xb20d 

#define CAM_YENDL       0xb20e 
#define CAM_YENDH       0xb20f 

/*		USB interface REGISTERS		*/
#define USB_REG_INDEX   0xb400
#define USB_REG_DATA    0xb401 
#define USB_EPCTRL      0xb402 
#define USB_EPFIFO      0xb403 
#define USB_IFCTRL      0xb404 
#define USB_COUNT_H     0xb405 
#define USB_COUNT_L     0xb406 

/*		LCD REGISTERS		*/
#define LCD_CON         0xB300
#define LCD_DATA        0xB301 

/*		Smart media REGISTERS		*/
#define SM_CONT         0xB410
#define SM_ADDR         0xB411 
#define SM_DATA         0xB412 

/*		IDMA REGISTERS		*/
#define DSP_PM_LOW      0xc000  // 2048
#define DSP_PM          0xd000  // 4096
#define DSP_DMC         0xe000  // 1024  
#define DSP_DMX         0xe800  // 2048 
#define DSP_DMY         0xf000  // 4096

/* register definistion for Handspring interface */
#define HANDSP_PIN_MUX          0xBA00
#define HANDSP_INTE_READY       0xBA01 
#define HANDSP_MODE_LOW         0xBA02 
#define HANDSP_MODE_HIGH        0xBA03 
#define HANDSP_STATUS_LOW       0xBA04 
#define HANDSP_STATUS_HIGH      0xBA05 
#define HANDSP_BLOCKSIZE_LOW    0xBA06 
#define HANDSP_BLOCKSIZE_HIGH   0xBA07 
#define HANDSP_GEN1_LOW         0xBA08 
#define HANDSP_GEN1_HIGH        0xBA09 
#define HANDSP_GEN2_LOW         0xBA0A 
#define HANDSP_GEN2_HIGH        0xBA0B 
#define HANDSP_GEN3_LOW         0xBA0C 
#define HANDSP_GEN3_HIGH        0xBA0D 
#define HANDSP_GEN4_LOW         0xBA0E 
#define HANDSP_GEN4_HIGH        0xBA0F 

/* register definition for Data flash */
#define DF_MODE             0xB800
#define DF_BANK_SET         0xB801 
#define DF_HS_LCD_MUX       0xB802 
#define DF_CMD              0xB803 
#define DF_ADD1             0xB804 
#define DF_ADD2             0xB805 
#define DF_ADD3             0xB806 
#define DF_BLOCKSIZE_LOW    0xB807 
#define DF_BLOCKSIZE_HIGH   0xB808 
#define DF_CLE_ALE_WAIT     0xB80A 
#define DF_RD_WE_WAIT       0xB80C 
#define DF_DMA_STATUS       0xB80D 
#define DF_UC_DOUT          0xB80E 
#define DF_UC_DIN           0xB80F 
#define CS_MUX              0x8043 

/* register definition for LCD interface */
#define LCD_MODE                0xBC00
#define LCD_INSTDATA_RDSTART    0xBC01 
#define LCD_DATA_OUT            0xBC02 
#define LCD_INST_OUT            0xBC03 
#define LCD_DATA_IN             0xBC04 
#define LCD_INST_IN             0xBC05 
#define LCD_READ_WAIT           0xBC06 
#define LCD_WRITE_WAIT          0xBC07 


// Constant related to Palm1

// define constant for USB interface and M5611 core

#define USB_EP0SIZE 						0x08
#define USB_EPASIZE 						0x40
#define USB_EPBSIZE 						0x08
#define USB_EPCSIZE 						0x08

/* M5611 Register Name */
#define USB_REG0_DEVICE_SETTING				0x00
#define USB_REG1_EP0_CONTROL				0x01
#define USB_REG2_EP0_FIFO 					0x02
#define USB_REG3_EPA_CONTROL				0x03
#define USB_REG4_EPA_FIFO 					0x04
#define USB_REG5_EPB_CONTROL				0x05
#define USB_REG6_EPB_FIFO 					0x06
#define USB_REG7_EPC_CONTROL				0x07
#define USB_REG8_EPC_FIFO 					0x08
#define USB_REG9_INT_ENABLE					0x09
#define USB_REGA_INT_FLAG					0x0A
#define USB_REGB_DEV_CONTROL				0x0B
#define USB_REGC_DMA_LR						0x0C
#define USB_REGD_DMA_HR						0x0D
#define USB_REGE_CHIP_VER					0x0E
#define USB_REGF_TEST_REG					0x0F
#define USB_REGG_ECH_CONTROL				0x10

/* INTERRUPT FLAG */
#define USB_INT_EP0TXD						0x80
#define USB_INT_EP0RXD						0x40
#define USB_INT_EPATXD						0x20
#define USB_INT_EPBRXD						0x10
#define USB_INT_EPCTXD						0x08
#define USB_INT_RESET						0x04
#define USB_INT_RESUME_SUSPEND				0x02
#define USB_INT_EOT_DMAR					0x01

/* Standard USB Command. Only Get Descriptor can be seen by software */
#define USB_CLEAR_FEATURE					0x01
#define USB_GET_CONFIGURATION				0x08
#define USB_GET_DESCRIPTOR					0x06
#define USB_GET_INTERFACE					0x0a
#define	USB_GET_STATUS						0x00
#define USB_SET_CONFIGURATION				0x09
#define	USB_SET_FEATURE						0x03
#define USB_SET_INTERFACE					0x0b

#define USB_VENDORCOMMAND					0x40

/* Descriptor Type */
#define USB_DESCRIPTOR_DEVICE				0x01
#define USB_DESCRIPTOR_CONFIG				0x02
#define USB_DESCRIPTOR_STRING				0x03
#define USB_DESCRIPTOR_INTERFACE			0x04
#define USB_DESCRIPTOR_ENDPOINT				0x05

/* Register bit mask definition */
#define USB_EP_EMP							0x80
#define USB_EP_FUL							0x40
#define USB_EP_FRC							0x20
#define USB_EP_INI							0x10
#define USB_EP_OVF_UNF 						0x08
#define USB_EP_SETUP						0x04
#define USB_EP_DIR							0x02
#define USB_EP_STALL						0x01

// define keypad constants
#define	KEYPAD_ROW			0x07
#define	KEYPAD_COLUMN		0x78
#define	KEYPAD_0			0x72	// 01110010
#define	KEYPAD_1			0x39	// 00111001
#define	KEYPAD_2			0x3a	// 00111010
#define	KEYPAD_3			0x3c	// 00111100
#define	KEYPAD_4			0x59	// 01011001
#define	KEYPAD_5			0x5a	// 01011010
#define	KEYPAD_6			0x5c	// 01011100
#define	KEYPAD_7			0x69	// 01101001
#define	KEYPAD_8			0x6a	// 01101010
#define	KEYPAD_9			0x6c	// 01101100
#define	KEYPAD_STAR			0x71	// 01110001
#define	KEYPAD_WELL			0x74	// 01110100
// When no key is pressed, the key value returned will be KEYPAD_NULL
#define	KEYPAD_NULL			KEYPAD_COLUMN

// define existing IRQ types
#define IRQ_CMDQ		0x00	/* command queue interrupt */
#define IRQ_DMA			0x01	/* dma interrupt */
#define IRQ_IO			0x02	/* i/o interrupt */
#define IRQ_CAMERA		0x03	/* camera interrupt */
#define IRQ_USB			0x04	/* usb interrupt */
#define IRQ_DSP			0x05	/* dsp interrupt */
#define IRQ_KEY			0x06	/* key interrupt */
#define IRQ_HANDSP		0x07	/* handspring interrupt */

#define INT_MASK_CMDQ		0x01	/* command queue interrupt */
#define INT_MASK_DMA		0x02	/* dma interrupt */
#define INT_MASK_IO			0x04	/* i/o interrupt */
#define INT_MASK_CAMERA		0x08	/* camera interrupt */
#define INT_MASK_USB		0x10	/* usb interrupt */
#define INT_MASK_DSP		0x20	/* dsp interrupt */
#define INT_MASK_KEY		0x40	/* key interrupt */
#define INT_MASK_HANDSP		0x80	/* handspring interrupt */

#define CLOCK1_MASK_CMDQ		0x80
#define CLOCK1_MASK_AC97		0x40
#define CLOCK1_MASK_PHILIPS		0x20
#define CLOCK1_MASK_TOFIFO		0x10
#define CLOCK1_MASK_FROMFIFO	0x08
#define CLOCK1_MASK_SDRAM		0x04
#define CLOCK1_MASK_DSP			0x02
#define CLOCK1_MASK_CON			0x01

#define CLOCK2_MASK_LCD			0x80
#define CLOCK2_MASK_FLASH1		0x40
#define CLOCK2_MASK_FLASH2		0x20
#define CLOCK2_MASK_EXTCLK		0x10
#define CLOCK2_MASK_USB			0x0c
#define CLOCK2_MASK_CAMERA		0x02
#define CLOCK2_MASK_IDMA		0x01

// define DMA constants
#define DMA_MASK_AC97_IN	0x02	// Channel 7, ac97 input
#define DMA_MASK_AC97_OUT	0x04	// Channel 6, ac97 output

// define memory constants
#define SRAM_START          0x6000	//
#define SRAM_DMA_START		0x7000	// 7000-71ff are used to exchange data between SDRAM and SRAM

#endif
